High TEC Copper to Connect Cu-Cu Pads for Wafer Bonding

Abstract

Introduction Cu/SiO2 hybrid bonding is a promising method for 3D stacking of integrated circuits in which the copper bonding of the interconnection pads and direct bonding of the silicon dioxide surface occur simultaneously.1 This bonding technology requires a damascene-like process on each sample to be bonded (wafers and/or chips), including copper deposition and chemical mechanical polishing (CMP), in order to create the copper bonding pads and lines.2 Due to the higher erosion rate of copper in comparison with silicon dioxide, a dishing effect on the surface of copper is generated. This effect can prevent bonding and thereby lead to electrical connection failure between top and bottom pads. In order to overcome this dishing effect and enhance the copper bonding at lower temperature, we developed a high thermal expansion coefficient (TEC) electrodeposited copper.Result and discussionFigure 1 shows the thermal expansions of conventional copper (black line) and electrodeposited copper with the high TEC additives (red curve). For the conventional copper, the expansion length at 300oC is 69 μm. Meanwhile, the expansion length of high TEC copper at 300oC is 90 μm, 30% higher than conventional copper.Figure 2 shows the variation of contact area with annealing temperature for 4 nm dishing depth of circular copper pad for conventional copper and high TEC copper. Contact area values are calculated by the model in numerical study of C. Sart et al.3. Copper pad width is 4 μm and thickness is 500 nm. It can be easily seen that the contact area with high TEC copper is significantly higher than conventional copper. At 200oC, the contact area of conventional copper is only 63.5 %. Meanwhile, the contact area of high TEC copper is 93.6 %. Furthermore, 100% contact area is possible from 250oC for circular copper pads with dishing depth 4 nm.Reference Rebhan et al., 17th Electronics Packaging and Technology Conference Proceedings, 1-4 (2015).Beilliard et al., International Journal of Solids and Structures (2016). DOI: 10.1016/j.ijsolstr.2016.02.041 Sart et al., 6th Electronic System-Integration Technology Conference (ESTC) (2016). DOI: 10.1109/ESTC.2016.7764484 Figure 1