Abstract
A new VLSI implementation for a 197-bit finite field multiplier using redundant representation is presented. The proposed design uses a simple module designed in domino logic as the main building block for the multiplier. We have used .18/Ltm CMOS technology from TSMC for our design. The final multiplier design was successfully simulated at a clock rate of 1.82 GHz. The proposed multiplier is at least 190% more efficient compared to similar designs, considering the product of area and delay as a measure of performance. Large field size finite field multipliers which operate at high speeds, such as the proposed design, have applications in public key cryptography.
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