High-speed ultrasonic digital delay line design: A restatement of some basic considerations

Abstract

In the past, ultrasonic delay lines in digital storage applications tended to be designed for a maximum storage capacity compatible with losses in the delay medium in order to minimize the cost of access circuitry. This approach yielded capacities upward of 20 000 bits per delay line but necessitated complicated arrangements to fold up the relatively long delay path in an acceptable space. It also required delay materials with a low ultrasonic propagation loss and accurate temperature stabilization, and resulted in comparatively long average access times to a given bit of information in the store. The emergence of inexpensive access and retiming circuits, however, suggests that delay line stores may be made at lower expense by subdividing them into modules of smaller capacity, and regenerating and retiming the bit stream it each module. This approach leads to design considerations different from the previous approaches and causes requirements of mechanical precision and temperature stability to be lowered. The design procedure described predicts that with presently available materials delay lines can be built which store about 1000 bits at bit rates in excess of 100 MHz, with insertion losses at band center of less than 20 dB and spurious signal suppression of at least 20 dB. Such lines have a storage density of more than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> bits per inch <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> .