Abstract
In this paper high speed Residue Number System (RNS) based FIR filter using Distributed Arithmetic (DA) is proposed. The proposed architecture uses the module set having the value of numbers as small as possible. In case of using Distributed Arithmetic in FIR filter; the size of LUTs gets increased exponentially with the increase of tap of the filter. Here care has been taken so that sizes of LUTs do not get increased. The propooed architecture is designed using verilog HDL; a popular hardware description language [9]. The design is synthesized with ISE 10.1 and implemented on Xilinx's Virtex-4. The propooed architecture is also compared with conventional RNS-DA FIR filter. The results show that the proposed architecture can implement FIR filter with high speed.
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