High-Speed Reset Waveform for PDP With Erase Address Discharge

Abstract

We propose a new high-speed reset waveform which uses a negatively biased voltage to the common electrode and an alternating ramp voltage to the scan electrode during the reset period and an erase address scheme. It showed a less than 800-ns time lag, a wide address margin over 40 V, and improved jitter characteristics among different color cells in a plasma display panel with a 50-in full-high-definition resolution. Its fast discharge characteristics were attributed to the formation of a higher wall voltage near the middle of the gap during the reset period and the consequent bigger electric field during the scan period which was confirmed by the 3-D emission observation and cell-voltage-domain analysis.