High-speed performance of 0.35 μm CMOS gates fabricated on low-dose SIMOX substrates with/without an N-well underneath the buried oxide layer

Abstract

We present experimental results concerning the propagation delay time of the 0.35 μm CMOS gate chains (inverter, 3NAND, and 3NOR) fabricated on low-dose SIMOX substrates with and without the N-well formed underneath the buried oxide layer in the PMOS region. Using such experimental data as the capacitance voltage characteristics of the buried oxide layer, and the enhanced PMOS transistor drivability due to the negative back bias effect, we clarify the most essential factor of the high-speed performance of the CMOS/SIMOX circuits fabricated on a low-dose SIMOX substrate.