High speed optical interconnection using embedded PDs on electrical boards

As an alternative approach to current electrical interconnection technology, optical interconnections at high speeds offer several potential advantages including small footprint, simple system design (in comparison to transmission lines), and immunity to electromagnetic interference. There are a number of approaches to integrating optical signal paths in electrical interconnection substrates such as backplanes, boards, and modules. One approach utilizes the heterogeneous integration of thin film optoelectronic (OE) devices embedded in waveguides. Optical signals can be coupled in from external fibers or from thin film lasers integrated onto the substrate, propagated, distributed, and processed in a planar waveguide format, and then coupled from the waveguide to an embedded thin film photodetector by evanescent field or direct coupling. This approach achieves alignment through assembly and successive masking layers and thus minimizes alignment issues. In addition, the integrated optical signal distribution system can be integrated onto the electrical interconnection substrate after the substrate has been fabricated using post processing, thus, the board facility is not impacted through the integration of the optical links. In this paper, a discussion of the fabrication processes as well as coupling efficiency and speed measurement results for thin film InGaAs PDs embedded in polymer waveguides integrated onto Si substrates is included. These results are compared to theoretical estimates of the coupling efficiency, which was estimated using the finite difference beam propagation method.

An I/O bandwidth commensurate with a dramatically increasing on-chip computational capability is highly desirable. Achieving this goal using board-level copper interconnects in the future will become increasingly challenging owing to severe increase in high-frequency, skin-effect and dielectric loss, noise due to crosstalk, impedance mismatch, and package reflections. The solutions designed to overcome these deleterious effects require complex signal processing at the interconnect endpoints, which results in a larger power and area requirement. Optical interconnects offer a powerful alternative, potentially at a lower power. Prior work in comparing the two technologies has entailed overly simplified assumptions pertaining to either the optical or the electrical system. In this paper, we draw a more realistic power comparison with respect to the relevant parameters such as bandwidth, interconnect length and bit error rate (BER) by capturing the essential complexity in both types of interconnect systems. At the same time, we preserve the simplicity by using mostly analytical models, verified by SPICE simulations where possible. We also identify critical device and system parameters, which have a large effect on power dissipation in each type of interconnect, while quantifying the severity of their impact. For optical interconnect, these parameters are detector and modulator capacitance, responsivity, coupling efficiency and modulator type; whereas, in the case of electrical system, the critical parameters include receiver sensitivity/offset and impedance mismatch. Toward this end, we first present an optimization scheme to minimize optical interconnect power and quantify its performance as a function of future technology nodes. Next, on the electrical interconnect side, we examine the power dissipation of a state-of-the-art electrical interconnect, which uses simultaneous bidirectional signaling with transmitter equalization and on-chip noise cancellation. Finally, we draw extensive comparisons between optical and electrical interconnects. As an example, for bandwidth of 6 Gb/s at 100 nm technology node, lengths greater than the critical length of about 43 cm yields lower power in optical interconnects. This length becomes lower (making optics more favorable) with higher data rates and lower bit error rate requirement.

As the demand of high data rate increases, electrical interconnects on the board becomes a bottleneck for the overall system performance because of crosstalk, transmission line effects, clock skew, and timing jitter. Thus, considerable effort has been made to investigate alternatives to board-level electrical interconnect, such as optical interconnects. However, current board-level optical interconnects still have limitations such as board fabrication cost, optical loss, and alignment tolerance. In this paper we discuss an optical board-level interconnect that uses optoelectronic devices embedded in an optical waveguide, to provide a solution to for Giga-bit data range interconnect, on FR4 printed circuit board (PCB). FR4 PCB is an attractive candidate because it is low-cost and widely used technology. However, the design of electrical interfaces to the optical interconnect still faces all the challenges of FR4 PCB design. Therefore, careful design of electrical path by EM/Schematic co-simulation is inevitable to use the FR4 PCB for 10 giga-bit per second (Gbps) applications even with optical interconnect. From the results of the measurements and simulations provided in this research, we see that fully embedded optical interconnect is a feasible solution to replace the current board-level electrical interconnect in high speed digital systems, however, the design of the optical electrical interfaces remains a challenging part of the interconnect problem.

Significant opportunities exist for optical interconnections at the board, module, and chip level if compact, low-loss, high-data-rate optical interconnections can be integrated into these electrical interconnection systems. To create such an integrated optoelectronic/electronic microsystem, mask-based alignment of the optical interconnection waveguide, optoelectronic active devices, and interface circuits is attractive from a packaging alignment standpoint. This paper describes an integration process for creating optical interconnections which can be integrated in a postprocessing format onto standard boards, modules, and integrated circuits. These optical interconnections utilize active thin-film optoelectronic components embedded in the waveguide/interconnection substrate, thus eliminating the need for optical beam turning elements and their alignment, and providing an electrical output on the substrate from an optical interconnection. These embedded optical interconnections are reported herein using BCB polymer optical waveguides with embedded InGaAs-based thin-film inverted metal-semiconductor-metal (I-MSM) photodetectors on an Si substrate. These interconnections have been fabricated and tested, and the coupled optical signal from the waveguide to the embedded photodetector was theoretically modeled at 56.4%, which was supported by an experimental estimate of 47.8%. The measured full-width at half maximum of the electrical pulse from the MSM photodetector embedded in the waveguide was 16.73 ps for an input 500-fs optical laser pulse.

The interconnect has become a primary bottleneck in integrated circuit design. As CMOS technology is scaled, it will become increasingly difficult for conventional copper interconnect to satisfy the design requirements of delay, power, bandwidth, and noise. On-chip optical interconnect is therefore being considered as a potential substitute for electrical interconnect. Based on predictions of optical device development, electrical and optical interconnects are compared for various design criteria. The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect at the 22 nm technology node are approximately one tenth of the chip edge length.

We propose a new approach to the physical design of optoelectronic system-on-a-package (SOP) using optical waveguide interconnect technology. The objective is to improve the performance of SOP by replacing long distance electrical interconnects with optical waveguide interconnects. A new simultaneous optimization algorithm for module placement and routing of electrical and optical interconnects is introduced. It not only improves the performance of SOP, but reduces the simulation time. Even though a small portion of electrical interconnects are replaced with optical interconnects, more than 21% improvement of the SOP performance is achieved.

Significant opportunities are emerging for optical interconnections at the board, module, and chip level if compact, low loss, high data rate optical interconnections can be integrated into these electrical interconnection systems. This paper describes an integration process for creating optical interconnections which can be integrated in a postprocessing format onto standard boards, modules, and integrated circuits. These optical interconnections utilize active thin-film optoelectronic components embedded in waveguides, which are integrated onto or into the interconnection substrate, thus providing an electrical output on the substrate from an optical interconnection. These embedded optical interconnections are reported herein using BCB (Benzocyclobutene ) polymer optical waveguides in two different formats, as well as a third waveguide structure using a BCB cladding with an Ultem core. All of these waveguides were fabricated with InGaAs-based thin-film inverted metal-semiconductor-metal (I-MSM) photodetectors embedded in the waveguide layer, thus eliminating the need for beam turning elements at the output of the waveguide. These embedded interconnections have been fabricated and tested, and the coupling efficiency of the optical signals from the waveguides to the embedded photodetectors was estimated from these measurements. These measurement-based estimates are then compared to theoretical models of the coupling efficiency. Using the theoretical coupling efficiency model, variable coupling can be engineered into the interconnect design, thus enabling partial coupling for arrays of photodetectors embedded in waveguide interconnections.

There is a strong demand for optical interconnection technology to overcome bandwidth bottlenecks in high-end server systems. The interconnection speed in present systems is approaching 10 Gb/s, and higher-speed interconnections over 25 Gb/s are being discussed. To achieve such optical interconnections in commercial production, it is necessary to develop lower-cost and higher-speed optical transceiver modules. We propose a flexible printed circuit optical engine (FPC-OE) with a microlens-imprinted film and a polymer waveguide to achieve low-cost and high-speed operation. The microlens-imprinted film can be produced at low cost by using nanoimprint technology and can drastically reduce the optical loss of the FPC-OE with polymer waveguide. We successfully demonstrated error-free operation at 25 Gb/s with the fabricated optical transceiver that contains an FPC-OE, microlens-imprinted film, and a polymer waveguide.

As data rates increase, optical interconnections at the boards and substrate levels become interesting alternatives for high performance interconnections according to Miller (2000) and Horowitz et al. (1998). Optical interconnection using embedded thin film photodetectors (PDs) in polymer waveguides is a chip to chip optical interconnection implementation that offers high speed interconnections with the potential for high integration density. This paper reports upon the integration of independently optimized waveguides and embedded PDs onto a Si substrate that utilizes a different material for each of these three components in the integrated interconnection. For the first time, reported herein are comparative measurements of the impulse responses and coupling efficiencies for two different directly coupled waveguide structures with embedded thin film InGaAs-based photodetectors. The difference between these two structures is the position of the thin film photodetector in the waveguide core. This information enables the designer to optimize embedded active photodetector/passive waveguide interconnections, particularly for high speed or multi-drop applications.

Quantitative analysis on the computing performance improvement by parallel optical interconnection

High speed optical interconnections offer an attractive alternative to electrical interconnections, particularly when they can be integrated into electrical systems. In particular, waveguide signal distribution and optical to electrical (O/E) conversion are critical to the integration of optical signals into electrical systems. The integration and interfaces between waveguides and O/E devices is a topic under intensive study. One approach to the integration of optical interconnections into electrical systems is to use fully embedded thin film optoelectronic (OE) devices in planar lightwave components on electrical interconnection substrates. In this approach, the propagating optical signal from the optical waveguide can be evanescently or directly coupled into the embedded thin film OE devices based on the embedded structure. Efficient and high speed optical signal distribution and O/E conversion, such as those using planar channel polymer waveguides with embedded thin film photodetectors, are examples of optical interconnection critical functions that are optimally implemented in electrical systems. In this paper, a 1 by 4 thin film metal semiconductor metal (MSM) photodetector (PD) array is embedded in a 1 by 4 photoimageable polymer multimode interference (MMI) coupler. This optical distribution and E/O system was fabricated and experimentally characterized at a wavelength of 1.3 μm. The measured overall loss, including the propagation loss and splitting loss of the MMI coupler was -0.18 dB at λ = 1.3 μm.

The rapid scaling of microprocessor technologies has led to unprecedented advancements in processing speed and transistor density. However, as device dimensions shrink below the nanometre scale, traditional electrical on-chip interconnects face critical limitations including increased signal delay, power consumption, and reduced bandwidth. These challenges have emerged as major bottlenecks in the performance and energy efficiency of modern microprocessors, especially in multi-core and many-core architectures. To overcome these limitations, optical interconnects have gained significant attention as a high-performance alternative for on-chip and chip-to-chip communication. Optical interconnects offer key advantages such as higher data rates, lower latency, reduced power dissipation, and immunity to electromagnetic interference. The integration of optical components like waveguides, modulators, photodetectors, and silicon photonics within the chip architecture has the potential to revolutionize interconnect design by addressing the shortcomings of conventional electrical wiring. This paper explores the evolution of on-chip interconnects, comparing the performance, scalability, and integration challenges of electrical and optical solutions in scaled microprocessors. It also discusses emerging hybrid interconnect architectures that combine the strengths of both technologies. A comparison is made between electrical and optical interconnects for different design criteria, based on projections about the future of optical devices. Around a tenth of the length of the chip's edge is the crucial dimension beyond which optical connectivity becomes preferable to electrical interconnect at the 22 nm technological node.

Communication efficiency plays an important role in accelerating the distributed training of Deep Neural Networks (DNN). All-reduce is the crucial communication primitive to reduce model parameters in distributed DNN training. Most existing all-reduce algorithms are designed for traditional electrical interconnect systems, which cannot meet the communication requirements for distributed training of large DNNs due to the low data bandwidth of the electrical interconnect systems. One of the promising alternatives for electrical interconnect is optical interconnect, which can provide high bandwidth, low transmission delay, and low power cost. We propose an efficient scheme called WRHT (Wavelength Reused Hierarchical Tree) for implementing all-reduce operation in optical interconnect systems. WRHT can take advantage of WDM (Wavelength Division Multiplexing) to reduce the communication time of distributed data-parallel DNN training. We further derive the required number of wavelengths, the minimum number of communication steps, and the communication time for the all-reduce operation on optical interconnect. The constraint of insertion loss is also considered in our analysis. Simulation results show that the communication time of all-reduce by WRHT is reduced by 80.81%, 64.36%, and 82.12%, respectively, compared with three traditional all-reduce algorithms according to our simulation results of an optical interconnect system. Our results also show that WRHT can reduce the communication time of all-reduce operation by 92.42% and 91.31% compared to two existing all-reduce algorithms running in the electrical interconnect system.

Optical interconnects are promising approaches for future short-distance communications because electrical interconnects show severe limitations in terms of bandwidth and energy consumption. To replace electrical interconnects with optical interconnects at short distances, reducing the overall energy of optical interconnects is indispensable. As an energy-efficient optical receiver system, a "receiverless" system has been proposed, in which power-consuming electrical amplifiers can be eliminated. However, a photodetector (PD) with low capacitance and high responsivity is required. In this article, we propose a silicon (Si) hybrid PD with an ultrathin InGaAs membrane based on a slot waveguide, which enables low capacitance while maintaining high responsivity. In the proposed structure, the ultrathin InGaAs membrane can eliminate an InP taper; therefore, the fabrication process can be simple, and the strong light confinement in a slot waveguide can reduce the PD length, which results in a lower capacitance. On the basis of simulations and experiments, we successfully demonstrated a PD with a sufficiently low capacitance of 1.9 fF and high responsivity of 1.0 A/W, which paves the way for future optical interconnects at short distances.

Power dissipation between electrical and optical interconnects for high-speed inter-chip communication is compared. A power minimization strategy for optical interconnects is developed and its scaling trends are shown. Optical interconnect when compared with the state-of-the-art electrical interconnect yields lower power beyond a critical length (43cm at 6Gb/s and 100nm technology node). The critical length is fully characterized as a function of system requirements (bit rate and bit-error rate) and interconnect's end-device parameters (detector capacitance, receiver sensitivity and offset). Higher bit rates yield lower critical lengths making optical interconnects more favorable in the future.