Abstract
This article presents methods and circuits for synthesizing test signals in the time/frequency domain. An arbitrary signal is first encoded using sigma-delta modulation in the digital amplitude-domain and con- verted to the time or frequency domain through a digital-to-time converter (DTC) or digital-to-frequency converter (DFC) operation realized in software. In hardware, the resulting bit-stream is inputted cyclically to a high-order phase-locked loop (PLL) behaving as a time-mode reconstruction filter in the appropriate domain (time or frequency). A high-speed proto- type implementation consisting of a 4th order PLL built in 0.13 μm complementary metal oxide semicon- ductor (CMOS) process with an off-chip loop filter has been fabricated and used to generate signals at 4 GHz. The digital nature and portability of the phase/ frequency test signal generation process makes the proposed scheme compatible with the IEEE 1149.1 test bus standard and easily amenable to any testing environment: production, characterization, design-for- test (DFT), or built-in self-test (BIST).
Highlights
The ability to generate high-frequency test signals onchip that can be made to vary over frequency and phase under external program control provides a useful debug and diagnosis tool (Fig. 1)
A digital-to-time converter (DTC) can be seen as any device used to map a digital value to a timebased signal, similar to a digital-to-analog converter (DAC) in the voltage/amplitude domain
In [2], it has been shown that a phase-locked loop can be used as a reconstruction filter for DTCs
Summary
The ability to generate high-frequency test signals onchip that can be made to vary over frequency and phase under external program control provides a useful debug and diagnosis tool (Fig. 1). The sigma–delta encoded digital signal is converted to the time or frequency domain through a DTC or DFC process. The hardware implementation consists of only a periodic bit-stream containing the sigma–delta encoded phase or frequency signal and a PLL.
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