High speed multioutput circuits using adiabatic logic

Abstract

In VLSI, major power consumption is due to dynamic switching power and leakage power. Dynamic logic is used to reduce the switching power using pre charge technique, in that there is no direct connection between VDD and GND, in Precharge mode load capacitance was charged and in evaluation mode depend upon the charge in capacitance logic level is decided. Adiabatic logic has the advantage in case of leakage power reduction. In adiabatic logic there is no separate VDD supply, it takes from clock signal. When clock is low circuit will enters in to sleep mode i.e there is no VDD connected to hence there will be zero leakage current, when clock is high the circuit will do its normal operation. Hence by combining dynamic and adiabatic logic, the switching and leakage power will be reduced by 50% compared to static logics.