High-speed MOS gate array

Abstract

The dimensions of the fundamental gate cell were analyzed in the gate-array type masterslice LSI which utilized the DSA MOS process combined with two-level metallization technology. It was revealed that the optimum gate width was 80 µm in the 4-µm design rule, taking the total power dissipation of 3 W and the delay time below 2 ns into consideration. The delay times were measured from both the original design chip and the 80-percent linearly shrunk chips. In the shrunk chip operated at a 3-V lower supply, the average gate delay time of 1.5 ns was obtained at a lower dissipation of 1.2 mW/gate which gave three times better performance than the original design chip at 5-V power supply.