High-Speed MOS Gate Array

Abstract

The dimensions of the fundamental gate cell were analyzed in the gate-array type masterslice LSI which utilized the DSA MOS process combined with two-level metallization technology. It was revealed that the optimum gate width was 80 /spl mu/m in the 4-/spl mu/m design rule, taking the total power dissipation of 3 W and the deIay time below 2 ns into consideration. The delay times were measured from both the orginal design chip and the 80-percent linearly shrunk chips. In the shrunk chip operated at a 3-V power supply, the average gate delay time of 1.5 ns was obtained at a power dissipation of 1.2 mW/gate which gave three times better performance than the original design chip at 5-V power supply.