High Speed Low Power Radix 4 Approximate Booth Multiplier

Abstract

Many applications such as image processing and multipliers are resilient to inexactness or approximations in their underlying computations. This is the basic concept of approximate computation. The resulting degradation in output quality can be traded off to develop more energy efficient and high performance hardware systems. In this context, approximate circuit design is an emerging paradigm that has recently received considerable research attention. Many applications such as signal processing and image processing requires the use of multipliers in its core operating system. The fundamental objective of a multiplier is that it must be efficient in power and operate at high speed. The aim is to design the best possible radix 4 booth multiplier using approximate computing. The work proposed in this paper is an extended application to an existing and recent work in approximate adder design SARA which is an Accuracy Configurable Adder (ACA). A radix 4 approximate booth multiplier application is proposed in this paper which has significant improvement in power, speed and accuracy compared to the earlier approaches in approximate booth multipliers. The comparison is performed with the conventional radix 4 booth multiplier and there is a 72% and 17% reduction in power and delay respectively.