Abstract
A high-speed comparator with improved input referred offset is presented and analyzed in this paper. The proposed comparator is designed in low power TSMC CMOS technology with 1.2 V as power supply. Proposed comparator features low power consumption and dual offset cancellation technique. Minimum detectable input voltage is 52 μV and the measured propagation delay in this worst case input is equal to 219 ps. The power consumption is 755 μW in 1 GHz input frequency. Monte Carlo simulation unveils the standard deviation of the input referred offset is 723 μV.
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