High speed CMOS/SOS IC’s fabricated using x-ray lithography

Abstract

High-speed CMOS/SOS IC’s with 1 μm design rules have been fabricated using x-ray lithography and the negative resist COP at eight mask levels. The fabrication processes four ion-implantation steps and two plasma etching steps. The CMOS/SOS LSI test chip contains ring oscillators with gate lengths of 1, 2, 3, 4, 5, and 7.5 μm. Speed–power data from the ring oscillators are presented; time delay per stage as low as 185 ps was measured for the devices with 1 μm gate lengths. The x-ray source design and the mask technology are reviewed. Scanning electron micrographs of resist patterns and replicated thin-film patterns are presented to show characteristic edge definition and stop coverage of narrow lines. Preliminary reliability testing of finished IC’s is reported; data from thermal stress tests (105 rads from a 60Co source) are compared to similar data from devices fabricated using photolithography. We conclude that x-ray lithography is a viable technology for fineline LSI.