High-speed bus circuit methodology

Abstract

High-speed bus circuits are the key to high performance systems with built-in processors. However, conventional bus circuits with low power consumption suffer problems such as ringing and dips caused by reflection and, as a result, the bus transmission rate cannot reach 100 MHz. Lattice diagrams have been used to analyze bus circuits, but these only show the approximate reflection behavior and cannot graphically portray the relation between reflection timing and waveform distortion due to reflection. This paper introduces a bus circuit with non-power-consuming termination that can achieve data transmission speeds over 100 MHz, 2.5 to 3 times faster than conventional low-power bus circuits. The paper also proposes a newly devised lattice diagram that can graphically clarify the relation between reflection timing and waveform distortion due to reflection. A SPICE simulation was carried out to examine the data transmission rate for each bus circuit. It was experimentally confirmed that our bus circuit, with non-power-consuming termination, operates at a 167-MHz data transmission rate. © 1998 Scripta Technica. Electr Eng Jpn, 122(1): 49–59, 1998