Abstract
Due to the advance of dynamic random access memory (DRAM) technologies with the steadfast increase of density with aggressively scaled storage capacitors, the supply voltage has been lowered to under 1 V to reduce power consumption. The above progress has been accompanied by the increasingly difficult task of sensing cell data reliably. One of the essential methods to preserve sustainable data retention characteristic is to curtail the sub-threshold leakage current by using a negative voltage bias for the bulk of access transistors. This negative back-bias is generated by a back-bias voltage generator. This paper proposes a novel high-speed back-bias voltage (VBB) generator with a cross-coupled hybrid pumping scheme. The conventional circuit uses one fixed voltage to control the gates of discharge of the p-channel metal oxide semiconductor (PMOS) and transfer n-channel metal oxide semiconductor (NMOS), respectively. However, the proposed circuit adds an auxiliary pump, thereby able to control more aptly with a lower negative voltage when discharging and a higher positive voltage when transferring. As a result, the proposed circuit achieves a faster pump-down speed and higher pumping current at a lower supply voltage compared to conventional circuits. The H-simulation program with integrated circuit emphasis (HSPICE) simulation results with the Taiwan semiconductor manufacturing company (TSMC) 0.18 um process technology indicates that the proposed circuit has about a 20% faster pump-down speed at a supply voltage of voltage common collector (VCC) = 1.2 V and about 3% higher pumping current at VBB from −0.6 V to −1 V with the ability to generate a near 3% higher ratio of |VBB|/VCC at VCC = 0.6 V compared to conventional circuits. Hence, the proposed circuit is extremely suitable and promising for future low-power and high-performance DRAM applications.
Highlights
As semiconductor technology advances rapidly, dynamic random access memory (DRAM) density is escalating aggressively
Higher ratio of |VBB|/voltage common collector (VCC) at VCC = 0.6 V compared to conventional circuits
A lowerThe negative voltage and the pumping current are among whensimulations discharging andperformed a higher positive voltagesemiconductor when transferring, and the proposed circuit achieves were with the Taiwan manufacturing company (TSMC)
Summary
As semiconductor technology advances rapidly, dynamic random access memory (DRAM) density is escalating aggressively. The DRAM storage capacitor retaining data is getting smaller, and it is becoming increasingly difficult to sense the data reliably with very small charges in the storage node To tackle this issue, the cell sub-threshold leakage current in DRAM depicted in Figure 1 should be eradicated or maintained at the very minimum to ensure long-cycled, power-saving operations in DRAM. The cell sub-threshold leakage current in DRAM depicted in Figure 1 should be eradicated or maintained at the very minimum to ensure long-cycled, power-saving operations in DRAM To serve this purpose, back-bias voltage (VBB) generation technique has been used in high density DRAM technology. Based on the previously researched VBB generator circuits in which a cross-coupled hybrid pumping circuit with auxiliary pump [2,5,7] is used to make the circuits operate at high-speed and without threshold voltage loss, our work adapts this cross-coupled. The three conventional circuits are voltage introduced and discussed in conventional
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