High speed area efficient 1-bit hybrid full adder

Abstract

The main requirement of Very Large Scale Integration (VLSI) circuit is to be fast and low energy consumption. So, the analysis is done by optimizing the delay, which results in fast processing and low average energy consumed. In this paper, 1-bit hybrid full adder is designed using Complementary Metal Oxide Semiconductor (CMOS), transmission gate and pass transistor logic. The circuit is implemented on Cadence Virtuoso 6.1 tool in 180-nm technology with 1.8V supply voltage. The delay (14.32ps) is found to be very small with significant reduction in the Power-Delay-Product(0.904fJ). The number of transistors is reduced; resulting in area optimization. The proposed 1-bit hybrid full adder design is found to be very fast as compared to the previous existing full adder circuits.