High speed and memory efficient VLSI architecture of 2D 5/3 DWT using interlaced scan algorithm for JPEG2000

Abstract

2D 5/3 discrete wavelet transform (DWT) involving complexed computation and huge memory consumption is one of the key components for the lossless mode of JPEG2000. The interlaced scan algorithm (ISA) of 2D 5/3 DWT is proposed, which scans a N×N image data in the order of interlaced lines and columns to compute, and only N-depth transpose memory is needed. Compared with the best conventional methods, the transpose memory is reduced by 50%. Based on the proposed memory efficient algorithm, the high speed VLSI architecture is designed with the parallel and pipeline schemes used. The synthesis results using the library TSMC 0.18μm show that the frequency can reach 333MHz.