High speed and low power on-chip micro network circuit with differential transmission line

Abstract

This work presents a high speed and low power on-chip micro network circuit with differential transmission line for seamless intra- and inter-chip communication. A 4 Gbps pulse signal transmission was confirmed and an 8 Gbps pulse signal was confirmed at the receiver circuit in 0.35 /spl mu/m and 0.18 /spl mu/m CMOS process technologies, respectively. It is expected that over 10 Gbps signal transmission can be achieved by using sub-100 nm CMOS technologies. From the simulated results, the RLC differential transmission line is faster and has lower power consumption than the RC line.