High-Speed and Low-Power Design Techniques for TCAM Macros

Abstract

Ternary content addressable memory (TCAM) is an important component for many applications. For TCAM-based networking systems, the rapidly growing size of routing tables brings with it the challenge to design higher search speeds and lower power consumption. In this work, two techniques are proposed to realize high-performance and low-power TCAM for IP address lookup. One technique is the tree AND-type match-line scheme for high search speed. The other technique is the segmented search-line scheme for low power. The implemented 1.8 V 0.18 mum 256 times 128b TCAM macro achieves a 1.56 ns search time using a 1.42 fJ/bit/search of energy.