High Spatial Resolution SIMS Depth Profiling of Cr Dopant in CdSe Thin Film Transistors

Abstract

CdSe thin film transistors (TFTs) whose structure is illustrated in Fig. 1, have been fabricated with Cr source and drain electrodes having separations varying between 5 and 50 µm [1]. The thermal annealing process employed to activate the devices has been shown to cause diffusion of Cr from the electrodes into the CdSe layer in the gap, doping the film [1,2]. Auger electron spectroscopy [2] was unable to determine the detailed Cr distribution in the device. Since the conductivity behaviour of CdSe and other polycrystalline semiconductor TFTs depends critically on the doping level [3,4], an attempt was made to determine the Cr distribution across the source drain gap and throughout the depth of the CdSe film in annealed, operational devices.KeywordsDepth ProfilePrimary BeamThin Film TransistorTransistor StructureThermal Annealing ProcessThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.