Abstract
This paper proposes a high-performance down scaler to improve the quality of a down-scaled image using interpolation filter. It uses a non-linear phase property of the digital filter to reduce hardware complexity. The implemented architecture is composed of four blocks: (i) line memory, (ii) vertical scaler with interpolation filter, (iii) horizontal scaler with interpolation filter, and (iv) FIFO. It has been fabricated by using 0.65 /spl mu/m CMOS process.
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