High reliability in PHEMT MMICs with dual-etch-stop AlAs layers for high-speed RF switch applications

Abstract

We have conducted a thorough investigation on the long-term process reliability for our recently developed dual-etch-stop (DES) pseudomorphic high electron mobility transistor (PHEMT) process using the on-wafer-level accelerated DC and RF biased step stress test up to 320 °C channel temperature as well as package-level three-temperature constant stress lifetest. Devices studied are 0.9-μm-gate InGaAs PHEMTs with two silicon-doped AlAs layers as gate and channel etch-stop materials. High-temperature-operating-life (HTOL) test on our single-pole-double-throw (SPDT) switch products using this DES PHEMT process has also been performed. This article describes the detailed reliability experiments and compares the reliability results of this new DES PHEMT process against the standard non-etch-stop (NES) PHEMT baseline material. Extensive statistical analyses on the DES PHEMT devices derived an activation energy E a=1.4 eV and a mean-time-to-failure (MTTF) > 10 7 h at 125 °C, an order of magnitude better than our baseline NES PHEMTs. This study demonstrates and discusses the excellent reliability in the DES PHEMT process for wireless communications applications.