High‐Rate Planar SiO2 Deposition Using Magnetron Bias Sputtering

Abstract

A high‐rate bias sputtering technique, employing a planar magnetron cathode and RF power supplies with a phase shifter, was developed to form planar films with a high deposition rate and low device damage. Utilizing the system, both the deposition rate and the etch rate for resputtering were increased to several times higher than those in conventional method. The effects of substrate biasing and deposition temperature on film quality were examined. Deposition temperature showed a stronger effect than substrate biasing on film quality, e.g., on the film's Ar content, refractive index, and etch rate by a buffered etch solution. The technique was applied to provide the planar interlevel insulation between two level interconnections for MOS VLSI test devices and showed significant improvement in step coverage and patterning accuracy in the second level metallization. It was also observed that there is little damage caused by the planar deposition using this bias sputtering and it can be easily annealed out, making this technique applicable to MOS VLSI's.