High-Q on-chip inductors using extremely thick silicon dioxide and copper-damascene technology

Abstract

High performance on-chip inductors fabricated using extremely thick low-stress silicon dioxide (SiO2) as the interface layer and copper damascene technology on standard CMOS silicon substrate are presented. A warpage-free low-stress SiO2 layer up to 20 µm thick is deposited using a modified deposition process. The maximum quality factor of a 1.3 nH inductor has been improved by 160% (from 21 to 55) when the thickness of SiO2 increases from 0.3 to 15 µm.