High-Precision and Low-Power Offset Canceling Tri-State Sensing Latch in NAND Flash Memory

Abstract

As the density of NAND flash memory increases, high-precision and low-power sensing latch is demanded. One promising solution for improving read precision is the offset canceling sensing latch (OCSL). The OCSL samples the trip voltage and compensates for its offset, reducing the effective trip voltage variation by 26.5%. However, the OCSL suffers from three problems due to the short-circuit between VDD and GND: 1) energy consumption of 20.7 pJ in the sense phase, 2) additional energy consumption of 78.7 pJ in the sample phase, 3) risk of data corruption in sample phase. In this study, the offset canceling tristate sensing latch (OCTSL) is proposed that achieves highprecision and low-power read operation with die area overhead of 0.015% through three key features: 1) sense phase without shortcircuit between VDD and GND by adopting tri-state sensing latch, 2) sample phase without short-circuit between VDD and GND by adding the sensing node precharge, 3) couple-down phase to enable the adoption of the tri-state sensing latch by using sensing node coupling capacitor. Compared to the OCSL, the proposed OCTSL reduces the effective trip voltage variation by 43.4%, reduces energy consumption by up to 99.1% and 78.3% in the sample and sense phases, respectively, and eliminates the risk of data corruption in the sample phase.