Abstract
Wearable electroencephalograph (EEG) acquisition sys-tem puts forward higher requirements for analog front-end (AFE) circuit, such as offset tolerance, common mode (CM) suppression, low noise and power consumption. This paper introduces design challenges and electrical characteristics of wearable EEG acquisition, reviews the two main system architectures, and focuses on different circuit techniques to improve key performance metrics, including large dynamic range (DR), high input impedance (Z <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</inf> ), low noise, CM and electrode offset rejection.
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