High Power Self-Aligned, Trench-Implanted 4H-SiC JFETs

K Vamvoukakis,K Zekentes,A Stavrinidis,D Stefanakis,M Kayambaki,G Konstantinidis,A Fernandez

doi:10.1051/e3sconf/20171612001

Abstract

The process technology for the fabrication of 4H-SiC trenched-implanted-gate 4H–SiC vertical-channel JFET (TI-VJFET) has been developed. The optimized TIVJFETs have been fabricated with self-aligned nickel silicide source and gate contacts using a process sequence that greatly reduces process complexity as it includes only four lithography steps. A source-pillars sidewall oxidation and subsequent removal of the metallization from the top of the sidewall oxide ensured isolation between gate and source. Optimum planarization of the source pillars top has been performed by cyclotene spin coating and etch back. The effect of the channel geometry on the electrical characteristics has been studied by varying its length (0.3 and 1.2μm) and its width (1.5-5μm). The voltage blocking exhibits a triode shape, which is typical for a static-induction transistor (SIT) operation. The transistors exhibited high ON current handling capabilities (Direct Current density >1kA/cm2 ) and values of RON ranging from 6 - 12 mΩ•cm2 depending on the channel length. Maximum voltage blocking was 800V limited by the edge termination. The maximum voltage gain was 51. Most transistors were normally-on. Normally-off operation has been observed for transistors lower than 2μm channel width (mask level) and deep implantation.

Highlights

Power transistors based on wide band gap semiconductors are subject of intensive research the last decade
4H-SiC-based Metal-Oxide Semiconductor Field-Effect Transistor (MOSFETs), Bipolar Junction Transistors (BJTs) and JFETs have been considered as candidate devices since their technology is more mature than other transistor types
Towards this aim different lithographic approaches, metallization schemes, isolation dielectrics and gate implantation conditions have been tested. This effort resulted in the fabrication of SiC TI-VJFET with self-aligned nickel silicide source and gate contacts including only four to six lithography steps depending on the edge termination scheme

Summary

INTRODUCTION

Power transistors based on wide band gap semiconductors are subject of intensive research the last decade. Current gain values lower than 30 were obtained for a long time by various research groups This issue has been addressed successfully by performing special surface passivation based mainly on oxides [3]. The purpose of the present study was to thoroughly investigate all 4H-SiC SITs process steps with the ultimate goal to simplify as much as possible their fabrication Towards this aim different lithographic approaches, metallization schemes, isolation dielectrics and gate implantation conditions have been tested. This effort resulted in the fabrication of SiC TI-VJFET with self-aligned nickel silicide source and gate contacts including only four to six lithography steps depending on the edge termination scheme

DEVICE PROCESSING

DEVICE MEASUREMENTS

CONCLUSIONS