High-Performance Wrap-Gated InGaAs Nanowire Field-Effect Transistors with Sputtered Dielectrics.

Li-Fan Shen,Zai-Xing Yang,Ming Fang,Johnny C Ho,Edwin Y.B Pun,Takfu Hung,Senpo Yip

doi:10.1038/srep16871

Abstract

Although wrap-gated nanowire field-effect-transistors (NWFETs) have been explored as an ideal electronic device geometry for low-power and high-frequency applications, further performance enhancement and practical implementation are still suffering from electron scattering on nanowire surface/interface traps between the nanowire channel and gate dielectric as well as the complicated device fabrication scheme. Here, we report the development of high-performance wrap-gated InGaAs NWFETs using conventional sputtered Al2O3 layers as gate dielectrics, instead of the typically employed atomic layer deposited counterparts. Importantly, the surface chemical passivation of NW channels performed right before the dielectric deposition is found to significantly alleviate plasma induced defect traps on the NW channel. Utilizing this passivation, the wrap-gated device exhibits superior electrical performances: a high ION/IOFF ratio of ~2 × 106, an extremely low sub-threshold slope of 80 mV/decade and a peak field-effect electron mobility of ~1600 cm2/(Vs) at VDS = 0.1 V at room temperature, in which these values are even better than the ones of state-of-the-art NWFETs reported so far. By combining sputtering and pre-deposition chemical passivation to achieve high-quality gate dielectrics for wrap-gated NWFETs, the superior gate coupling and electrical performances have been achieved, confirming the effectiveness of our hybrid approach for future advanced electronic devices.

Highlights

In the past decade, III–V compound semiconductor nanowires (NWs) have attracted extensive amount of research and development interest due to their excellent physical properties for high-performance nanoelectronics and highly efficient photovoltaics[1,2,3,4,5,6,7,8,9,10]
Based on the plane spacing determination and the reciprocal lattice spots extracted by fast Fourier transform (FFT), the NW exhibits single-crystalline zinc-blende (ZB) structure with a dominant growth orientation in the direction, and no significant amount of stacking faults or twin-plane polytypic defects are found in the samples
WG nanowire field-effect-transistors (NWFETs) have been explored as an ideal field-effect transistors (FETs) geometry for low-power and high-frequency applications, the required performance improvement and practical device implementation still lag behind expectation, largely due to the electron scattering at the NW surface and/or interface traps between the NW channel and gate dielectric, and the complicated device fabrication scheme

Summary

Introduction

III–V compound semiconductor nanowires (NWs) have attracted extensive amount of research and development interest due to their excellent physical properties for high-performance nanoelectronics and highly efficient photovoltaics[1,2,3,4,5,6,7,8,9,10]. ~10 nm) high-k dielectric layer all over the NW, in which the resulting device characteristics are strongly affected by the obtained dielectric/NW interface qualities; as a result, atomic layer deposition (ALD) is typically employed for this critical dielectric coating step despite its high processing cost, long reaction time, and limited material choices for the dielectrics[26] Both vertical and lateral WG NW device configurations have been reported for InAs27–33. Wernersson et al provided a comprehensive investigation of vertical WG InAs NW field-effect transistors (FETs) with the HfO2 gate dielectric, delivering a maximum ON current density of 0.08 A/mm with an SS of 75 mV/dec at room temperature[34] This SS value is very close to the theoretical limit of SS = 60 mV/dec, indicating good control of channel electrostatics and interface properties. This superior capacitive gate coupling of WG InGaAs NWFETs confirms the versatility of our simplified WG device fabrication scheme using high-quality sputtered dielectrics, as well as the potential applications of InGaAs NW channels for future high-speed, low-power, and high-frequency electronic devices

Methods

Results

Conclusion