Abstract
Spin-orbit-torque magnetic tunnel junction (SOT-MTJ) is an emergent spintronics device with a promising potential. It resolves many issues encountered in the current MTJs state of the art. Although the existing Spin Transfer Torque (STT) technology is advantageous in terms of scalability and writing current, it suffers from the lack of reliability because of the common write and read path which enhances the stress on the MTJ barrier. Thanks to the three terminal architecture of the SOT-MTJ, the reliability is increased by separating the read and the write paths. Moreover, SOT-induced magnetization switching is symmetrical and very fast. Thus, doors are opened for non-volatile and ultra-fast Integrated Circuits (ICs). In this paper, we present the architecture of a mixed CMOS/Magnetic non-volatile flip-flop (NVFF). We use a compact model of the SOT device developed in Verilog-A language to electrically simulate its behaviour and evaluate its performances. The designed standard cell offers the possibility to use the usual CMOS flip-flop functionality. In addition, it enables storing and restoring the magnetic data by exploiting the non-volatility asset of MTJs when the circuit is powered off. With a 28nm dimension, the SOT-MTJ based NVFF demonstrated a very high speed switching (hundreds of picoseconds) with 7× decrease in term of writing energy when compared to the STT device.
Highlights
Technology innovations are mainly motivated by the worldwide tenders around them
In order to simulate the switching behavior of the SOT-Magnetic Tunnel Junction (MTJ), we developed a compact model written in Verilog-A language which is on the path to becoming the preferred compact modeling language for both academic and industrial research groups
Since the interest of MTJs is greater at advanced technology nodes and in order to be more faithful to the macrospin assumptions used in the macro-model, we investigate the SOT and Spin Transfer Torque (STT) devices at 28 nm dimension
Summary
Technology innovations are mainly motivated by the worldwide tenders around them. Portable computing and connectivity have a continuous market demand. The last decade, the limits of conventional device scaling are fronting major problems, such as leakage current, performance saturation, acute device variability and process complexity Trying to overcome these hurdles, several solutions are studied at technology, circuit and architecture levels. The first generation of NV MRAM is magnetic-field controlled known as Field Induced Magnetic Switching (FIMS) [3] This approach suffers from selectivity and scalability issues. We introduce a macrospin compact model that we developed in Verilog-A language to describe the behaviour of the SOT-MTJ device and enable its integration into semiconductor commercial design flows to realize hybrid CMOS/magnetic ICs. Simulations results show the great potential of SOT-MTJ to improve the writing energy compared with STT-MTJs for a non-volatile flip-flop (NVFF) study case.
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