High‐performance semistatic TSPC DFF

Abstract

Reduction of the size and the power consumption of the DFF, the component that has the largest area occupancy in the standard cell, is extremely useful for the reduction of the same characteristics in the entire chip. The proposed DFF is a semistatic configuration realizing True-Single-Phrase Clocking (TSPC). In comparison with the conventional circuit, this one is successful in reduction of power consumption and in improvement of circuit characteristics such as noise endurance. Also, even though the number of NMOSs is almost twice that of PMOSs, the lateral pitch is less than in the conventional small DFFs fabricated with the 0.25-μm SIMOX, bulk, and MT-CMOS low threshold process common layout, by virtue of a layout in which only the NMOSs are multistaged. The standard cell blocks designed with the proposed DFF are fabricated by a 0.25-μm SIMOX process. The power consumption is computed by measurement of the supply current. It is found that the power consumption is reduced by 23% on average in comparison with circuits using the conventional DFF. © 1999 Scripta Technica, Electron Comm Jpn Pt 2, 82(3): 22–30, 1999