High performance package designs for a 1 GHz microprocessor

Abstract

This paper describes the architecture and design of an Organic Land Grid Array (OLGA) and a Flip Chip Pin Grid Array (FCPGA) package for a 32 bit microprocessor with a clock frequency of 1 GHz and an I/O bus designed to run at 133 MHz. Cost and performance targets and compatibility with existing systems are the key accomplishments of this design project. Issues and implementation details of each of these aspects are discussed and contrasted here. There are many items in design which directly or indirectly impact package cost: I/O timings, signal trace impedance, number of routing layers, power delivery, thermal performance, and silicon and system level interface, among others. Often, trade-offs need to be made in the design to balance performance and cost. OLGA and FCPGA technologies have differences in package substrate material, manufacturing process, and platform interface. The OLGA package has a 4-layer organic laminated substrate, copper conductors, low dielectric constant insulators, high density interconnect rules for routing and silicon connectivity, and surface mounting capability for the system interface. The FCPGA package, a 6-layer laminated printed circuit board with blind microvias and buried, plated through hole (PTH) vias, has a relaxed set of interconnect and routing rules, and enables direct socketability for system interface. This paper concentrates on the processor performance issues associated with the package routing and power delivery. Due to high inductance associated with the socket and package pins in the FCPGA package, power supply loop inductance was a concern for high frequency power delivery. To overcome this problem, a certain number of decoupling capacitors were placed on the underside of the package substrate. This paper discusses an optimal placement scheme for the capacitors and their effectiveness in performance improvement of the system compared to the OLGA package case.