High performance, low power CMOS memories using silicon-on-sapphire technology

Abstract

Silicon-on-sapphire (SOS) technology allows the fabrication of complex MOS integrated circuits with high speed performance comparable to that of bipolar circuits but at the expense of only microwatts of quiescent power dissipation. The use of a 1 µm thick single crystal silicon films allows virtual elimination of the parasitic capacitance which seriously degrades the performance of bulk silicon MOS circuits. Complementary MOS/SOS integrated circuits fabricated with self-aligned silicon gate technology and 5 µm channel spacings make 2 nanosecond gate delays and 1 picojoule gate power x delay products possible at 5V operation. In addition to high switching speed and low dynamic power, CMOS/SOS circuits with low leakage currents and therefore low quiescent power can be fabricated. The reverse currents of vertical junction SOS diodes are due to electron-hole generation in the depletion layer and have the voltage dependence predicted by the Sah-Noyce-Shockley theory. Lifetimes on the order of 1 ns have been measured; however, the total junction leakage currents are small (50 pa/mil width at 5 V) due to the extremely small junction areas involved.