Abstract
In this paper, a high-performance parallel pipelined hardware structure of Volterra decision feedback equalizer (Volterra-DFE) for 4-level pulse amplitude modulation (PAM-4) transmission is derived and implemented for the first time. For feed-forward portion, an approach based on multi-level register banks is employed, and the feedback portion is pipelined by converting complex calculation in the loop into the form of pre-computation and multiplexer. To facilitate field programmable gate array (FPGA) implementation, this paper also studies the bit error rate (BER) performance of a low-complexity Volterra-DFE to explore the minimum feedback tap setting that can reach the forward error correction (FEC) threshold, and the experimental results show that for a three-order Volterra-DFE with 61 feed-forward taps, at least 7 feedback taps are required and the received sensitivity is −19 dBm. The resource utilization of the implemented FPGA architecture is investigated and its throughput can reach 24-Gb/s, which is of great significance to real-time optical communication systems.
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