High Performance LDPC Decoder design using FPGA

Abstract

LDPC codes are an important aspect of 5G communication systems. This paper presents high performance design of Low-density parity-check decoder on reconfigurable FPGA. LDPC codes are one of the most efficient error correcting codes for implementation on FPGA. The main aim is to implement a low complexity architecture of the LDPC decoder on the FPGA (Field Programmable Gate Array). The two main components of LDPC are VNU and CNU. Our efficient decoding structure will reduce the complexity with the help of check node unit (CNU) and the variable node unit (VNU) using min-sum algorithm for getting fewer slice resources. Here, we have used multiplexed storage structure for storing nod message to get the result in minimum FPGA resources. LDPC is quite an integral part in deep space communications and its potential utilization in the area which is highly explored. In space data systems it is quite important to have a LDPC decoder which has both low complexity and high performance architecture. Therefore the low-complexity method becomes an efficient method to achieve the requirements put in future by many wired and wireless communication system.