Abstract
Programmable Logic Controllers (PLC) are used in industry for automation. Now-a-days it is a standard practice to include safety interlocks along with logic functions in the PLC programming. The use of smart sensors also gives very fast changing inputs to the PLC. This makes the response time of PLC an important issue. The scan time of PLC depends upon two parameters viz. the length of PLC program and operating frequency of CPU. Thus, in order to improve PLC response time, it is necessary that scan time of PLC should be less. This paper suggests an IEC 61131-3 standards compatible PLC application dedicated Instruction List (IL) processor with a three-stage instruction pipeline on FPGA platform for better response time.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.