Abstract
Programmable Logic Controllers (PLC) are used in industry for automation. Now-a-days it is a standard practice to include safety interlocks along with logic functions in the PLC programming. The use of smart sensors also gives very fast changing inputs to the PLC. This makes the response time of PLC an important issue. The scan time of PLC depends upon two parameters viz. the length of PLC program and operating frequency of CPU. Thus, in order to improve PLC response time, it is necessary that scan time of PLC should be less. This paper suggests an IEC 61131-3 standards compatible PLC application dedicated Instruction List (IL) processor with a three-stage instruction pipeline on FPGA platform for better response time.
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