High performance embedded system for real-time pattern matching

C.-L Sotiropoulou,P Luciano,S Gkaitatzis,S Citraro,P Giannetti,M Dell'Orso

doi:10.1016/j.nima.2016.06.030

Abstract

In this paper we present an innovative and high performance embedded system for real-time pattern matching. This system is based on the evolution of hardware and algorithms developed for the field of High Energy Physics and more specifically for the execution of extremely fast pattern matching for tracking of particles produced by proton–proton collisions in hadron collider experiments. A miniaturized version of this complex system is being developed for pattern matching in generic image processing applications. The system works as a contour identifier able to extract the salient features of an image. It is based on the principles of cognitive image processing, which means that it executes fast pattern matching and data reduction mimicking the operation of the human brain. The pattern matching can be executed by a custom designed Associative Memory chip. The reference patterns are chosen by a complex training algorithm implemented on an FPGA device. Post processing algorithms (e.g. pixel clustering) are also implemented on the FPGA. The pattern matching can be executed on a 2D or 3D space, on black and white or grayscale images, depending on the application and thus increasing exponentially the processing requirements of the system. We present the firmware implementation of the training and pattern matching algorithm, performance and results on a latest generation Xilinx Kintex Ultrascale FPGA device.

Highlights

Pattern Selection Definition pi : probability pattern “i” in sample image set Ntot : total number of patterns N : number of stored patterns W : available bandwidth H : measure of output information
Algorithm Sequence [2]: 1° Stage Training: calculate the frequency and entropy of each pattern in the sample images/frames to select the relevant patterns to be used as reference for the matching process 2° Stage Run: send the image patterns to AM chip to be filtered matching the relevant patterns The AM chip is a CAM like Associative Memory Chip (ASIC) that executes pattern matching in parallel [3]
It can be seen that the filtered images (b) and (c) obtained with the selection of “relevant patterns” are recognizable, while in image (d) filtered with low probability patterns, the important features are lost

Summary

Algorithm Description

Pattern Selection Definition pi : probability pattern “i” in sample image set Ntot : total number of patterns N : number of stored patterns (available memory space) W : available bandwidth H : measure of output information. Algorithm Sequence [2]: 1° Stage Training: calculate the frequency and entropy of each pattern in the sample images/frames to select the relevant patterns to be used as reference for the matching process 2° Stage Run: send the image patterns to AM chip to be filtered matching the relevant patterns The AM chip is a CAM like ASIC that executes pattern matching in parallel [3]. Patterns that are efficient carriers of information given the bandwidth (W) & memory limits (N) [2]

Pattern Selection and Impact on Output pixel b a

Hardware Setup

Findings

Simulation and Implementation Results a b c