High performance chip to substrate interconnects utilizing embedded structure

Abstract

Integrated circuit (IC) feature sizes reaching nanoscale range, it is important to bridge the gap between modules and chips with design rules similar to that of IC fabrication technologies. A proper transition calls for improved interconnect design and embedding of IC's to preserve signal integrity. This paper presents a high performance packaging approach for state-of-the-art high frequency IC's (HFIC's). Evaporation-, sputtering- and liftoff procedures were adopted to create smooth, fully planar Au-Cu-Au metallization on low dielectric constant (k) substrates utilizing a dual-mode transmission line in order to decrease microwave losses in carrier interconnects. A special attention was put to investigation of via hole formation.