High-performance built-in self-routing for through-silicon vias

Abstract

In this reported work, a built-in self-routing scheme is developed for exploring the through-silicon via (TSV) redundancy to the extremes. A built-in self-router consists of a built-in self-tester for testing the TSVs, and a priority switching network for selecting from M TSVs to N inter-chip interconnects. A switching cell is developed to sequentially construct the priority switching network for area reduction and synthesis regularity. Although a long latency is needed for the encoding network, the best performance during inter-chip communication can be achieved due to only one switch per tier in normal operations. In a multiple fault model with no more than M−N defected TSVs, the repair rate can be always 100%.