High-performance and ultra-compact spike-based architecture for real-time acoustic echo cancellation

Abstract

In recent years, the implementation of advanced adaptive filters in embedded devices for acoustic echo cancellation has increased because most of them are used in portable devices, especially in Internet of Things systems, in which high-performance and low-area digital hardware implementations are required. In this work, we present a high-performance and ultra-compact spike-based hardware architecture to efficiently compute adaptive filters to be used as an acoustic echo canceller (AEC). To achieve this architecture, we address two factors. (1) We propose a new data-selective adaptive filter along with subband decomposition least mean square (LMS) method to reduce the computational cost by minimizing the number of operations required to efficiently update the filter coefficients. The proposed method requires approximately 40% fewer updates when compared with conventional subband adaptive filters. As a consequence, the spike-based hardware architecture simulates the proposed adaptive filter at high processing speeds. (2) We propose a compact and high-precision neural multiplier since acoustic echo cancellers require a large number of high-precision multiplications to efficiently identify the echo path. The proposed neural multiplier expends up to 15 times fewer synapses when compared with existing approaches, which represents a significant improvement in terms of area. In addition, this improvement avoids routing problems by implementing large-scale synapse connectivity in advanced FPGAs. Herein, we carry out exhaustive testing by simulating several acoustic echo scenarios. The results demonstrate that the features of the model and the hardware implementation techniques potentially allow easy integration into portable devices for use in real-world acoustic echo cancellation scenarios.