High performance and low power transistors integrated in 65nm bulk CMOS technology

Zuying Luo ,C Wann,J Sudijono,D Vietzke,A Vayshenker,K Lee,L Kim,B Zhang,F Jamin,S Kim,V Ku,R Rengarajan,P Shafer,E Kaltalioglu,P Wrschka,C Coppock,M Eller,D Park,V Chan,R Mo,P Nguyen,J Lian,M Hoinkis,M Weybright,K Kim,A Ajmera,A Cowley,Ja Chun Ku ,Wee Chong Tan ,I.y Yang ,T.b Hook ,Hao Zhu ,Christopher Baiocco ,Sajan Marokkey ,T Schiml ,Wei Lin ,An Steegen ,Velveth Klee ,Yo‐Sheng Lin ,R W Mann ,Sunny Fang

doi:10.1109/iedm.2004.1419254

High performance and low power transistors integrated in 65nm bulk CMOS technology

Zuying Luo , C Wann + Show 39 more

https://doi.org/10.1109/iedm.2004.1419254

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Publication Date: Dec 13, 2004

Citations: 48

Affiliation: Samsung (South Korea), Semiconductor Research Corporation, Infineon Technologies (Canada), IBM (United States)

#High Performance Power #High Performance CMOS Devices + Show 8 more

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Abstract

This paper reports a cutting-edge 65nm CMOS technology featuring high performance and low power CMOS devices for both general and low power applications. Utilizing plasma nitrided gate oxide, off-set and slim spacers, advanced co-implants, NiSi and low temperature MOL process, well designed NMOSFET and PMOSFET achieved significant improvement from the previous generation, especially PMOSFET has demonstrated an astonishing 35 % performance enhancement from the previous technology node

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