High performance and low‐power finite impulse response filter based on ring topology with modified retiming serial multiplier on FPGA

Abstract

In this study, a low-power and high performance architecture for finite impulse response digital filter based on the ring topology which is modelled from recurrent neural network is presented. The proposed structure is based on a ring topology reduced number of multipliers, adders and also CLK cycles. In the design, all the operators including multipliers and adders have been designed at gate level. Multiplication is a very important operation in many digital filters hence, the authors designed a novel and modified retiming serial multiplier. To increase the performance, the authors use two types of adders, a proposed high-speed logarithmic carry look ahead adder and a carry save adder with four inputs. The proposed structure is modelled and verified using FPGA and simulation results. It has been successfully synthesised and implemented with Xilinx ISE 7.1 and Virtex IV FPGA, target device Xc4vf100. The results demonstrate that the proposed method has high performance and low-power consumption.