High Performance 3-2 Compressors Architectures for High speed Multipliers

Abstract

The 3-2 compressor is widely used in broad range of applications. Its main application is in partial product addition of multipliers. In this paper new architectures for 3-2 compressors which are having less power consumption, less time delay and less number of transistors than the conventional architectures, are presented. The proposed architectures use pass transistors, transmission gates and domino logic circuits. All the circuits used in the proposed architectures have better performance characteristics than that of CMOS circuits and existing compressors. The loss of voltage swing caused by the use of pass transistors is negated by the use of transmission gates and domino logic circuits after the pass transistors. The proposed 3-2 compressors offer 66–82% less power and 52 to 64% reduction in propagation delay. Simulation are done with Synopsis HSPICE tool. Therefore, high performance of the proposed 3-2 compressors makes them a good option for efficient multiplier designs.