High Open Circuit Voltage Gain in Vertical InGaAs Channel Metal-Insulator-Semiconductor Field-Effect Transistor using Heavily Doped Drain Region and Narrow Channel Mesa

Abstract

We fabricated a vertical metal–insulator–semiconductor field-effect transistor (MISFET) with a heterostructure launcher and an undoped channel. Vertical MISFETs exhibit a high drain current density; however, their large output conductance is a disadvantage for the open-circuit voltage gain. In a previous study, a maximum voltage gain of 4.0 was found in a vertical MISFET with a heavily doped drain region and a 45-nm-wide channel mesa. The heavily doped drain region and a narrower channel width are effective in reducing the output conductance. In this study, we fabricated a device with the heavily doped drain region and a 23-nm-wide channel mesa structure. It was observed that the output conductance decreased from 120 to 57 mS/mm at a drain current density of 0.3 MA/cm2 with a narrower channel mesa. The maximum open-circuit voltage gain increased from 4.0 to 5.7.