High-Linearity Direct Conversion Receiver with the Transconductance Equalization Technique and DCOC Method

Yiming Han,Zhiyu Wang,Jiarui Liu,Fengjie Wang,Faxin Yu

doi:10.3390/electronics10161966

Abstract

To improve the linearity of direct conversion receivers (DCRs), two high-linearity methods for high second-order intercept points (IP2s) and high third-order intercept points (IP3s) are proposed. To improve IP3s, a transconductance equalization technique for a complementary input operational amplifier (OPAMP) is proposed in an active-RC low-pass filter (LPF), while a digital-analog hybrid DC offset calibration (DCOC) method is proposed to improve IP2s. For one thing, the proposed transconductance equalization technique employs a pair of resistors to guarantee high voltage gain for an OPAMP with two-stage Miller topology under a high-input voltage swing to improve linearity with little deterioration of the noise performance. For another, during the DCOC method, the low-noise amplifier is turned off and replaced by an equivalent resistance of the output impedance of the low-noise amplifier to ensure the accuracy and effectiveness of the DCOC method. Fabricated in 40-nm CMOS technology, the receiver with proposed methods can realize a noise figure of 2.6–3.5 dB in the full frequency band, with an OIP3 of 28 dBm, an IM2 more than 70 dBc, and a remaining DC of −53.2 dBm under the total voltage gain of 60 dB.

Highlights

40-nm CMOS technology, the receiver with proposed methods can realize a noise figure of 2.6–3.5 dB in the full frequency band, with an OIP3 of 28 dBm, an IM2 more than 70 dBc, and a remaining DC of
For a high IP3, an RC-active filter is the preferred topology when achieving high linearity is the most critical design metric, because RC-active filters can realize high linearity and be capable of supporting a large voltage swing based on an operational amplifier (OPAMP) with finite high gain and bandwidth [2]
This paper presents two high-linearity methods for a direct conversion receivers (DCRs) to realize better IP2 and

Summary

Introduction

40-nm CMOS technology, the receiver with proposed methods can realize a noise figure of 2.6–3.5 dB in the full frequency band, with an OIP3 of 28 dBm, an IM2 more than 70 dBc, and a remaining DC of. For a high IP3, an RC-active filter is the preferred topology when achieving high linearity is the most critical design metric, because RC-active filters can realize high linearity and be capable of supporting a large voltage swing based on an operational amplifier (OPAMP) with finite high gain and bandwidth [2]. Several works have been reported to improve the linearity of the RC-active filters by employing OPAMPs or OTAs with multi-stage topologies and compensated structures to realize high loop gain [3,5,6,7,8,9], while some solutions considered low-voltage and low-power applications [10,11]. The loop gain of a multi-stage topology can be limited by a large voltage swing. Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations

Methods

Results

Conclusion