High K Metal Gate CMP Process Development for 32nm and Beyond Gate Last Approach

Abstract

ILD0 CMP and Al CMP plays important roles to form high k metal gate in the gate last approach for 32nm technology and beyond. It requires very tight control for the gate height and the surface topography. The gate height uniformity improvement, the dishing/erosion reduction and defect reduction are the key aspects for ILD0 CMP and Al CMP process development. Firstly, the polishing strategies and slurry selection are the most critical part. Several types of SiN slurries for ILD0 CMP process are evaluated. The impacts of SiN slurry's selectivity on dishing and poly thickness control are studied. The pros and cons of different CMP techniques, such as fixed abrasive CMP and slurry CMP for ILD0 CMP will be elaborated as well. Secondly, the pattern design and the design rules have significant impact on gate CMP process performance. The gate height and topography performance for different feature sizes and pattern densities are described and the dummy rule setup strategies are explored in this paper. Next, defect (Al pitts, scratches, particles, residues and as such) is another major challenge to a successful gate CMP process. The mechanism for the formation of the various types of defects is discussed and approaches for defect reduction are explored. In addition, the interation among the STI CMP, ILD0 CMP and Al CMP processes is discussed. Lastly, various process control and gate height monitor methods are compared and discussed in this paper.