Abstract
A layout to minimize parasitic elements which reduce the common emitter Heterojunction Bipolar Transistor (HBT) gain and efficiency is described. Layout modifications are based upon consideration of the HBT device model that predicts better performance by reducing feedback elements. Reducing the base contacts size to minimize extrinsic base-collector capacitance, and reducing inductance in the ground connection are the primary paths to better performance. The improvements in small signal and power performance for several HBT variations are described. The changes result in a 320 μm 2 emitter area HBT which operating pulsed at 10 GHz delivers 1.25 W output power with 10.5 dB associated gain and 56% power-added efficiency.
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