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Abstract
This paper reports on the transistor design of high-speed SiGe HBTs with low parasitic resistances and capacitances. Elevated extrinsic base regions and a low-resistance collector design were integrated in a SiGe:C BiCMOS technology to simultaneously minimize base and collector resistances and base-collector capacitance. This technology features CML ring oscillator delays of 3.6 ps per stage for HBTs with f T/ f max values of 190/243 GHz and a BV CEO of 1.9 V.
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