Abstract
Circuit design techniques for realizing high-frequency, low-power phase-locked loops (PLLs) in monolithic silicon bipolar technology are discussed. A varactor-tuned voltage-controlled oscillator (VCO), an analog phase detector, and a bandgap reference have been utilized as building blocks. A test circuit fabricated in a 2- mu m bipolar process exhibited a maximum center frequency of 350 MHz, and the PLL pull-in range was larger than +or-1%. The circuit operates from a 5-V supply and dissipates 270 mW. >
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
