Abstract
Rapid increase in operating frequencies and power density necessitate the importance of examining electromagnetic compatibility/electromagnetic emissions (EMEs) from high-frequency and high-power integrated circuits (ICs). In this paper, a simulation method is demonstrated to study the EME using gallium nitride high electron mobility transistor power amplifier IC chip as a device under test. Simulation model is developed by collaborating a high-frequency structure simulator with a Keysight Advance Design System for simulation of three-dimensional layout of IC. The simulated EME results are verified with experimental measurement results; the hotspots obtained with higher EME as identified by a near-field scanner and simulation results are identical. With this simulation method, optimization is done using a response surface methodology to reduce the EME for the IC chip. It is found that small changes in the IC layout can make a significant difference in the EME. Simulation model developed with RSM optimization technique opens a gateway for the IC industry to investigate EME of their chip design without going through a costly and time-consuming process of fabrication for testing its EME.
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